Strained-si Technology for Rf Power Ldmosfet

This thesis studied the application of strained-Si technology to RF power LDMOSFETs. Key issues for its implementation were determined to be thermal budget restrictions, gate oxide formation and impact ionization effects. 2D simulations were carried out to explore the design space of the strained-Si LDMOSFET. In order to address the thermal budget restrictions, use of a high-tilt implant for the body doping was investigated. For a dose of 1.5x10 1 3cm 2 , the conditions for the body implant that resulted in the best output characteristics, as determined by gm, DIBL and ro, were 50 keV energy with a tilt of 60'. The major trade-off of the n-drift region was that of breakdown vs. on-resistance. Loss of strained-Si in CMOS during the gate oxide formation was found to be a potential issue for System-on-Chip (SOC) applications. Two options for the implementation of a 10 nm gate oxide were assessed. Option one was a 750 'C dry/wet/dry thermal oxidation on a thick strained-Si layer. Option two was a composite oxide consisting of a thin dry oxidation followed by an LTO deposition. Capacitor structures were fabricated and tested. Both options exhibited good characteristics as determined by C-V, leakage and Dit measurements. TLM structures were fabricated to investigate impact ionization effects in the strained-Si/SiGe heterostructure. Preliminary analysis of the structures show that there is a significant difference in II generation between the control bulk Si and strained-Si samples. For the same source current levels, the strained-Si samples had body current that was an order of magnitude higher than bulk Si. Lower saturation current levels were observed in the strained-Si structures compared to bulk Si. Self-heating had an effect in the strained-Si samples but was not thought to be solely responsible for the lower current levels. Thesis Supervisor: Jesu's A. del Alamo Title: Professor of Electrical Engineering